Sowjanya Palagani

Embedded Systems Engineer around 3 years of experience in performance profiling, power optimization, and low-level firmware development across Qualcomm Snapdragon and automotive SoC platforms. Skilled in ARM Cortex-A/M architectures, Linux kernel/RTOS optimization, and power-aware design methodologies. Proven expertise in system performance tuning, thermal/power analysis, and embedded software debugging using industry tools.

Adept at collaborating with cross-functional hardware, firmware, and validation teams to improve power efficiency by up to 30% and enhance real-time responsiveness for consumer and automotive devices.

Embedded Performance & Power Optimization Engineer - Qualcomm Technologies Inc. - USA

(2025-01)

• Spearheaded SoC-level performance and power optimization across Snapdragon 8-series platforms, analyzing CPU/GPU/DDR workloads with Perf, LTTng, and OProfile to reduce total system power by 28% while maintaining throughput benchmarks.
• Designed and implemented Dynamic Voltage and Frequency Scaling (DVFS) algorithms for multiple compute domains, achieving balanced power-performance tradeoffs and extending battery life by up to 30 minutes per charge cycle on reference devices.
• Developed and integrated thermal-aware scheduling and CPUfreq tuning policies within the Android kernel, improving user interface responsiveness by 20% under sustained high-load conditions.
• Conducted real-time system tracing and bottleneck identification using Trace32 and LTTng, diagnosing ISR latencies, cache-miss hotspots, and contention in memory controllers; collaborated with firmware engineers to reduce interrupt delays by 18%.
• Partnered with silicon design teams to perform power modeling correlation between RTL simulations and post-silicon measurements using RAPL/PTM traces, ensuring less than 5% variance between pre-silicon projections and measured data.
• Created Python-based automation scripts for profiling and regression testing, streamlining power/thermal validation cycles across 200+ builds and cutting manual analysis time by 45%.
• Contributed to bootloader (U-Boot) and PMIC driver optimization, refining boot-time power sequencing and initialization routines, resulting in 15% faster system startup with lower transient current peaks.
• Collaborated with cross-functional groups (hardware, kernel, BSP, and QA teams) in Agile sprints, improving build stability and verification coverage of power features across multiple SoC generations.
• Authored detailed SoC performance analysis reports and power tuning guidelines, establishing best practices adopted globally by 5+ Qualcomm design teams to enhance future chipset designs.
• Supported lab power measurement and validation, instrumenting boards with Power Analyzer and logic analyzers to capture transient loads, validate sleep states, and ensure compliance with mobile power KPIs.
• Mentored junior engineers on power/performance tradeoff analysis, driving continuous improvement in firmware efficiency and scalability across embedded product lines.

Embedded Software Engineer - HCL Tech - Andhra Pradesh, India

(2021-09 - 2023-07)

• Engineered and optimized embedded C/C++ system software for client projects across automotive, storage, and server platforms, delivering high-performance and reliable solutions tailored to customer requirements.
• Led system-level profiling and performance analysis using tools such as OProfile, Tracealyzer, and custom telemetry frameworks, identifying CPU, memory, and I/O bottlenecks and improving end-to-end latency by 20%+ across real-time and distributed embedded workloads.
• Designed and implemented core OS components—including task scheduling, memory management, and interrupt handling—on FreeRTOS and Linux-based platforms, enhancing system determinism, throughput, and stability for time-critical applications.
• Contributed to virtualization and storage integration initiatives, architecting and optimizing data-path components for VMware VVols and related storage virtualization workflows to improve scalability and provisioning efficiency.
• Developed Python-based automation frameworks for performance, power, and scalability validation, integrating 70+ automated test scenarios into CI/CD pipelines (Jenkins) and reducing validation effort by 30–35%.
• Optimized system startup and peripheral subsystems by refining boot-time initialization, clock trees, DMA-driven drivers, and communication stacks (SPI, UART, I2C, CAN, Ethernet), resulting in faster boot cycles and improved communication robustness.
• Collaborated with hardware and platform engineering teams to configure SoCs, server infrastructure, power sequencing (PMIC), and low-power states, achieving 25%+ power efficiency gains while meeting performance SLAs.
• Designed and executed end-to-end scalability, stress, and HIL (Hardware-in-the-Loop) testing for embedded and enterprise solutions, validating system behavior under dynamic load, thermal variation, and fault-injection scenarios.
• Customized Yocto and Buildroot-based BSPs, integrating kernel patches, drivers, and performance instrumentation to support reproducible builds, regression testing, and multi-platform customer deliverables.
• Conducted embedded security assessments and threat modeling aligned with MITRE ATT&CK and industry best practices, identifying vulnerabilities and implementing mitigation strategies for safety-critical and industrial environments.
• Authored detailed design documentation, performance reports, and root-cause analyses to support compliance requirements (including ISO 26262) and to drive continuous improvement in system reliability and performance.

Masters - Kennesaw State University (2023-08 - 2025-05)

Bachelors - Lakireddy Bali Reddy College of Engineering (2019-05 - 2023-05)