USC VLSI Master’s graduate seeking ASIC/CPU Design Verification roles with experience in SystemVerilog, UVM, processor verification, patents, and AI-driven research.
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Graduate Research Assistant at USC
Computer Architecture Design and Verification
ASIC design
Graduate student at USC
Pursuing master degree of Analytics at USC
ECE @ USC
Design Verification
Verification Engineer using SV UVM
Design Verification Engineer
Verification Specialist
