Director of Process Engineering, Head of Process - CDimension - San Jose, CA
(2026-03 - 2026-06)
- Led a cross-functional team to develop epitaxial growth of WSe2 for P-MOS and MoS2 for N-MOS devices on silicon and sapphire substrates utilizing CVD/ALD processes.
- Directed the transition from laboratory-scale processes to cleanroom operations by coordinating facility, hardware, field service, and process teams to install and commission pumping systems, wafer handling systems, LoadLocks, front-end systems, and process modules.
Sr. Process Engineering Manager - Applied Materials - Santa Clara, CA
(2022-07 - 2025-12)
- Achieve an extremely low contact resistance gap-fill (>45% lower than the POR process in the logic applications) with breakthrough innovation (Pre-clean/PVD/CVD/ALD, patent filed) for the MoL integration solutions.
- Utilize the plasma, CVD/ALD Mo concepts to (1) develop the PM procedure (2) improve the Tput to ~8.9 WPH w/o comparing resistivity @ 100 A (3) improve Resistivity to ~17 uohm-cm w/t Tput ~4 WPH for 100 A.
- Lead and corporate across MOL/KAT/HW/SW/GPS teams to investigate/solve the integration risks of the W, Mo, Ti, TiSi, and MoSi deposition processes and pre-clean process.
- 15 technology patents filed and two C&F products within three and half years Sr. Manager level.
Sr. Staff Process Engineer - Applied Materials - Santa Clara, CA
(2019-09 - 2022-06)
- Scope/Lead the next oxidation generation module/system product roadmap, which meets customers' requirements for the N+2, N+3, and future technology roadmap.
- Understand and solve the oxidation conformality issue (~70%) to achieve a high conformality (>99%) in the 3D NAND features (AR >150).
- Coordinate software/hardware engineers and key account team members to finalize & achieve the criteria of a highly selectivity oxidation process (to SiN and W).
Staff Process Engineer - LAM Research Corp. - Fremont, CA
(2017-01 - 2019-09)
- Innovated the thermal Incubation Control Enhancement (ICE), which integrated with the low-stress ALD/CVD-W for the two tiers 3D NAND MC gap-fill improvement (SC>200% @10 um depth features) in a single module.
- Integrated Altus-W CVD deposition and the Nitrogen plasma-based ICE treatment processes and achieved the SC-130% @ 6 um depth features.
- Handled and solved process/hardware escalations from customers by detailed root cause analysis, troubleshooting, and executing correct hardware/software process modifications. The Manufacturing tool uptime is enhanced ~20-30% uptime.
- Cooperated with the KAT/HW/SW teams and customers to define the criteria of the next generation deposition tool and solved unexpected issues/escalations, managed project/task schedules, and met the requirements.
Senior Process Engineer - LAM Research Corp. - Fremont, CA
(2015-01 - 2017-01)
- Developed an ExtremeFill to enable Dcp1/Etch/Dcp2 for W-Film fill improvement for 2x nm nodes in memory and x nm node in logic applications. Achieved void-free fill, reduced 20% contact resistance, and improved 30-50% of throughput. Lam selected this achievement as one of the 2015 Lam Vista Awards.
- Succeeded to complete tool startup and developed a tungsten process, which met customer integration scheme within a week. The tungsten process was qualified for customer POR. Customer was satisfied with the results and placed orders for their production line.
- Developed a low-temperature thermal Fluorine free ALD process with ~100% conformality performance.
- Optimized work-function of Fluorine free barrier layer in memory applications to meet customer integration requirements, like electrical performance and reliability.
- Integrated the Fluorine free barrier with bulk W-CVD to achieve good plug fill, low Rc and stress, and smooth W.
Process Engineer - LAM Research Corp. - Fremont, CA
(2011-04 - 2015-01)
- Developed a low-temperature thermal Fluorine free ALD process with ~100% conformality performance.
- Optimized work-function of Fluorine free barrier layer in memory applications to meet customer integration requirements, like electrical performance and reliability.
- Integrated the Fluorine free barrier with bulk W-CVD to achieve good plug fill, low Rc and stress, and smooth W.
Research & Development Engineer, Device Technology and Development Division - Winbond Electronics Corporation - Hsinchu, Taiwan
(2006-11 - 2007-07)
- Experience in defining the design rule of process schemes for logic applications. Troubleshoot the electrical failure and resolve the failure by improving the process flow scheme.
- Documented the design rule for 0.13 um process generation.
- Improved yield performance by troubleshooting electrical failures/physical characterization.
Research Assistant - North Carolina State University, Department of Materials and Engineering - NC
(2007-08 - 2011-03)
- Broad understanding of several functional oxide/compound materials, such as VO2, ZnO, PZT, TiOx, MgO, YSZ, In2O3, and NiO.
- Successfully characterized structures and properties of the epitaxial film by XRD, SEM, TEM/EDX, UV-visible, and electrical measurements.
- Effectively reviewed collaborative projects, interacted with coworkers in experimental design/conducted experiments.
Research Assistant - National Tsing-Hua University, Department of Materials and Engineering - Hsinchu, Taiwan
(2002-09 - 2004-06)
- Deep understanding of "Thermodynamics and Metal behavior" to design a novel glass alloy (high entropy alloy), ZrTaTiNbSi.
- Successfully deposited the amorphous alloy at room temperature by physical sputtering on the high entropy alloy target of ZrTaTiNbSi.
- Comprehensive understanding the thermal stability, mechanical/electrical properties, and atomic level crystallization in amorphous film varying with the annealing temperatures.
