Embedded Design Engineer at GOWell International (2024-07 – Present)
- Developed and validated C firmware for a wireline logging tool operating above 150°C, performing system-level debugging across firmware, sensors, FPGA interfaces, and telemetry to improve reliability and reduce tool failure rates to 0.106%.
- Engineered FreeRTOS on dsPIC33E for deterministic real-time scheduling; implemented side-band control sequencing and HW-SW interfaces across embedded hardware blocks.
- Tested firmware functionality through integration, thermal, and QC validation workflows; post-processing in Python to analyze sensor data, flag threshold failures, and support pass/fail decisions during V&V stages.
- Developed and validated analog front-end and digital comms (SPI, I2C), LVDS-based SPI conversion, CAN bus packaging and diagnostics; debugged firmware using Microchip debuggers and oscilloscopes to reproduce, triage, and resolve issues.
Graduate Assistant Teaching at Texas A&M Engineering Experiment Station (2023-01 – 2024-01)
- Managed and instructed laboratory sessions for over 60 undergraduate students in Circuit Analysis.
DFT Engineer (Intern) at Synopsys Inc (2022-05 – 2022-12)
- Developed PHY RTL for high-speed proprietary IP (USB/PCIe), enabling efficient ATE testing and pre-silicon SoC diagnosis.
- Automated ATPG pattern generation, tool execution, and HSIO packetization using Bash/Shell and Python scripts, improving repeatability and test efficiency with TestMAX ALE.
- Streamlined JTAG TAP-based testing, significantly reducing GPIO requirements and enhancing SoC validation effectiveness.
- Built and optimized testbenches for AXI/SCAN loopback tests, strengthening RTL verification processes.
Graduate Assistant Research at Texas A&M Engineering Experiment Station (2021-09 – 2022-05)
- Awarded a full research scholarship: proposed a framework to enhance the security of Cyber-Physical Systems (CPS), advocating for FPGA encryption enhancements; shared the impactful findings with ACM Computer Survey Journal.
Embedded Design Engineer at OPOLO Cosmos (2020-04 – 2021-07)
- Achieved EAL 6+ certification for OPOLO Hardware Wallet by developing secure C firmware on STM32, and protected communication interfaces for authenticated data exchange with Android and desktop applications with AES-CMAC.
- Designed and implemented Password Manager/Mnemonics-Backup on RFID cards with efficient flash memory management, earning recognition in Forbes' 10 Most Cutting Edge Wallets of 2020.
- Enhanced UX and security by optimizing touchscreen drivers using LVGL (C++), strengthening secure element integration, and improving memory management on the ARM Cortex M4 platform.
