Design verification
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I am a Entry-Level / Graduate Design Verification Engineer .
I have strong fundamentals in digital electronics, Verilog, SystemVerilog, UVM, SVA, functional coverage, and constrained-random verification. I am also familiar with protocol-based verification involving APB, AXI, SPI, I2C, FIFO-based designs, and basic DDR memory controller concepts such as command flow, bank operation, row/column addressing, refresh, read/write transactions, and timing parameters.
I have hands-on practice in building UVM testbench components including sequence items, sequences, drivers, monitors, agents, scoreboards, environments, and test classes. I am comfortable with waveform debugging, regression analysis, assertion-based checks, coverage-driven verification, Linux/Git usage, and Synopsys VCS simulation flow.
As a fresher, I am highly motivated to learn, improve, and contribute to real ASIC/SoC/IP verification projects. I am looking for an opportunity where I can apply my verification skills, grow under experienced engineers, and contribute to high-quality pre-silicon verification work.
Thank you for considering my application. I would be grateful for the opportunity to discuss how my skills and learning mindset can contribute to your verification team.
design verification
