Haopu Yao

I am an ECE post-graduate student from University of Toronto currently enrolled in Meng program.

On-Chip Design with a 4-Bit Mix-Signal MAC Array Sep. 2022 – Dec. 2022

• Assigned corresponded activation and weight to composite analog signal based on deep neural networks logic. 
• Built up multiple 6T-SRAM to store 7x4 bits weight for multiply-accumulate array.
• Created a binary combiner reconstructing output analog signal based on each assigned weight.
• Designed a SAR ADC to convert modified analog signal into digital 8 bits output. 
• Finalized all project components layout on a Padframe by TSMC’s 65nm technology.

• Implemented TSMC’s 65nm technology to analyze and modify signal delay at different stages for an inverter chain. 
• Constructed a circuit schematic diagram and layout for the designed circuit simulation.

• Wrote Verilog to construct 4x4 bit multipliers with CPA and CSA.
• Run synthesis to test multiplier logic, and generate timing and power consumption report.
• Automatically constructed the layout diagram of multiplier by Innovus.

Electrical & Computer Engineering-MEng Sep. 2021 - Present

University of Toronto

• Currently enrolled in Integrated Circuits for Digital Commnication (ECE1392) and RF IC design (ECE1390F).
• Focus on Analog/Digital Circuit Design, Embedded System, Electrical Wireline Communication(PHY), and Digital