Jay Park

Digital Verification Engineer with 4 years of experience in firmware verification, FPGA validation, and digital verification for consumer and enterprise electronics. Hands-on experience in FPGA bring-up and hardware debug for PCIe, USB, Ethernet, and SERDES-based products, with strong exposure to RTL analysis, assembly-level debug, simulation-based verification, UVM testbenches, functional coverage, and assertions. Proven ability to develop and enhance regression, debug, and testcase scripting flows to improve validation efficiency and support high-quality firmware and digital design releases.

Digital Verification Engineer - Synopsys

(2026-01 - 2026-05)

• Performed digital verification for PCIe 6 designs, developing a strong understanding of architecture, key features, and technical highlights.
• Worked with UVM-based testbench environments to support feature verification and debug.
• Contributed to verification quality using functional coverage and SystemVerilog assertions.
• Performed RTL and gate-level simulations on PHY and firmware releases to investigate issues and support debug.

FPGA Validation / Firmware Verification Engineer - Synopsys

(2022-07 - 2025-11)

• Performed FPGA bring-up and firmware verification for Ethernet, PCIe, and USB SERDES products.
• Debugged behavior directly on FPGA hardware to validate firmware functionality and understand hardware/software interaction.
• Used RTL, assembly files, DVE simulations, Identify Debugger, and MATLAB to investigate issues and accelerate debug.
• Developed and modified regression, debug, and testcase scripts to improve test environment capability and validation efficiency.
• Supported validation across PCIe Gen1 / Gen2 / Gen3 / Gen4 and USB feature sets on various channels

Bachelor of Electrical Engineering - Carleton University (2022)