About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable lead
Job Description SiFive is seeking a hardware design engineer who is passionate about designing industry‑leading debug, trace and profiling IP to help drive the tidal wave of adoption of RISC‑V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creati
A leading technology firm is seeking a hardware design engineer in La Ciotat, France, to develop industry-leading debug, trace, and profiling IP for RISC-V architecture. The ideal candidate should have over 7 years of experience in RTL design and possess strong knowledge in debug architectures and h
Il y a 4 jours
Salaire estimé pour Debug à La Ciotat
23 000 € – 36 000 €/an
Confiance de l'estimation : Basse
Estimation basée sur les données du marché pour La Ciotat. Les salaires réels peuvent varier selon l'expérience, l'entreprise et la zone.