Midhul M S

Product Validation and Debugging Engineer with 3 + years of semiconductor product validation experience at UST on Intel programs, delivering analytics, validation, and root-cause investigation for complex embedded systems. Hands-on with WPA, ETW, GPU Trace, Event Viewer, and code-level debugging in C/C++, with added exposure to embedded platforms including Arduino and 8051.

Built

Python tools and KPI dashboards that improved reporting visibility, supported a 15% driver performance gain, and helped deliver 95% on-time execution across cross-functional work streams. Currently pursuing an MSc digital business analytics at EMLV Paris, bringing strong programming fundamentals, international work culture experience, and a practical, detail-oriented approach to solving technical problems. Actively seeking a 6-month internship from June to November 2026 to apply my expertise and enhance my education.

Associate I – Semiconductor Product Validation at UST Global (Client: Intel) (2023-01 – 2024-12)

• Defined validation plans and executed V&V test campaigns for embedded GPU, display, and media software.
• Identified, reported, and tracked anomalies, then summarized results in test reports.
• Built KPI dashboards and Python tools to improve analysis speed and reporting visibility.
• Improved driver performance by 15 % through automation and defect analysis.
• Collaborated with product, QA, deployment, and R&D teams on compliance and improvement.

Semiconductor Debug Engineer at UST Global (Client: Intel) (2022-01 – 2023-12)

• Tested and analysed complex embedded systems across different hardware using WPA, ETW, GP Trace, and Event Viewer.
• Escalated root-cause findings and actionable recommendations to engineering teams, supporting issue resolution ahead of delivery deadlines.
• Contributed to debugging pipelines for GPU and display driver validation, reducing defect leakage rates.

Semiconductor Triage / Validation Engineer at UST Global (Client: Intel) (2021-01 – 2022-12)

• Designed and executed comprehensive test plans for GPU and display validation across multiple hardware configurations.
• Partnered with development and QA teams to track high-priority issues, corrective actions, and reproducibility status in agile sprint cycles.
• Achieved 95% on-time delivery across cross functional project work streams through proactive issue tracking and stakeholder communication.

IT Support Engineer at M.S. Constructions & Contractors (2019-01 – 2021-12)

• Managed hardware maintenance, software configuration, and end-user troubleshooting for a multi-site construction firm.

MSc in Digital Business & Analytics (M1) – EMLV (École de Management Léonard de Vinci) (2025-09)

MCA in Master of Computer Applications (BAC+5) – Amrita Vishwa Vidyapeetham (2017-01 – 2019-12)

BCA in Bachelor of Computer Applications – Amrita Vishwa Vidyapeetham (2014-01 – 2017-12)