Muhammad Ijaz

Senior FPGA Design Engineer with a Master's in Electronics Engineering and strong expertise in VHDL, Verilog, and DSP algorithms. Experienced in developing efficient, high-performance FPGA solutions with a focus on quality and innovation. Seeking to contribute to advanced design projects in a dynamic engineering environment.

Senior FPGA Engineer - SWARM - Prince Sattam Bin Abdulaziz University - Al-Kharj, Saudi Arabia

(2024-04)

• System-level FPGA architectures for real-time radar processing pipelines ensuring scalability and deterministic performance
• Designed external DDR memory interfaces and managed multi-clock domain designs with proper CDC techniques for timing-critical radar processing pipelines
• Performed timing closure and critical path optimization for high-speed FPGA designs under strict real-time constraints
• Utilized on-chip debugging tools such as ILA for root-cause analysis of complex FPGA design issues
• Optimized FPGA resource utilization including LUTs, BRAM, and DSP slices for high-efficiency implementations
• Developed performance benchmarking models to evaluate latency, throughput, and pipeline efficiency of signal processing chains
• Integrated RF transceivers such as AD9361/4 and ADRV9009/2 with FPGA platforms for high-speed SDR and radar applications
• Designed and validated high-speed ADC/DAC and transceiver interfaces ensuring synchronized for data acquisition
• Led hardware-software integration testing across FPGA and embedded software layers for end-to-end system validation
• Implemented structured verification flows using simulation-based testbenches for corner-case validation of DSP modules
• Maintained version-controlled FPGA development workflow using Git for collaborative and traceable design management
• Contributed to system design documentation including architecture specs, interface definitions, and validation reports
• Collaborated with RF engineers to optimize signal chain performance and minimize system-level latency
• Ensured signal integrity and EMC compliance considerations during high-speed FPGA board-level integration

FPGA Design Engineer - National Radio & Telecommunication Corporation (NRTC) - Haripur, Pakistan

(2019-04 - 2024-03)

• Designed and implemented Verilog/VHDL-based algorithms for 2D beamforming on FPGA platforms
• Developed modular and reusable custom IP cores using VHDL/Verilog for scalable FPGA designs
• Implemented DSP algorithms including FFT/IFFT, FIR filters, DDS, CORDIC, and frequency detection for SDR systems (AD9361)
• Architected FPGA-based real-time systems for multi-channel (100+) data acquisition and processing
• Developed C-based FFT and embedded applications using Xilinx SDK for hardware acceleration
• Designed signal generation modules supporting LFM, HFM, and CW waveforms for RF applications
• Implemented high-speed communication interfaces including UART, SPI, I2C, AXI, AXI-DMA, and Ethernet
• Integrated PS-PL communication using AXI protocol and DMA for efficient data transfer
• Developed QT-based GUI applications for embedded systems such as spectrum analyzers, ventilators, and RF jammers
• Performed MATLAB-based DSP algorithm design, modeling, and validation
• Conducted RTL design, synthesis, and implementation using Xilinx toolchain for RF and wireless communication systems
• Collaborated with cross-functional teams to deliver end-to-end FPGA solutions aligned with system requirements

Higher Education Research Assistant - University of Engineering and Technology Taxila - Taxila, Pakistan

(2017-09 - 2019-03)

• Conducted extensive literature review on Stochastic Computing digital systems covering theory, applications, and recent advancements
• Implemented stochastic computing architectures on FPGA (Artix-7), demonstrating hardware design expertise
• Designed stochastic computing based FIR filters in MATLAB for multiple filter orders with simulation validation
• Delivered lectures on FPGA design and circuit analysis as visiting faculty for undergraduate engineering students

Internship - National Institute of Electronics - Islamabad, Pakistan

(2017-04 - 2017-09)

• Implemented VHDL/Verilog designs using Xilinx ISE and Vivado tools for FPGA development workflows
• Gained exposure to Cadence HDL verification tools and fundamental PCB design using Altium Designer
• Learned industrial FPGA development lifecycle including design entry, synthesis, simulation, and verification

MS - Electronics Engineering - University of Engineering and Science and Technology Taxila (2017-09 - 2021-03)

BS - Electronics Engineering - The Islamia University of Bahawalpur (2012-11 - 2016-11)