Digital Hardware & FPGA Engineer
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Engineer bridging wireless DSP/PHY and digital hardware. I take algorithms from MATLAB/Python to synthesizable RTL and lab bring-up.
M.Sc. project: LTE-A/5G OFDMA receiver.
Research: 2 IEEE papers on Wi-Fi 6E/7 (Multi-AP, Multi-Link) with Intel Labs.
Industry: FPGA verification (RTG4/GR740) at Airbus Crisa; spread-spectrum military modems on Xilinx at Sener.
Stack: VHDL/Matlab, Vivado/Questa, test automation in Python/TCL.
FPGA/DSP engineer focused on wireless and defence systems.
Sener Aerospace & Defence (2024–present) — Communications FPGA Engineer. Design & verify spread-spectrum military modems (Xilinx; VHDL). Python/TCL test automation.
Airbus Crisa (2023–2024) — FPGA Verification Engineer. Coverage-driven verification for space-grade RTG4/GR740, CDC/constraints.
University of Oviedo – 5G Chair (2022–2023) — Low-latency 5G testbeds (OAI), HW/SW integration.
IKERLAN (2020–2022) — Wireless PHY/MAC research; 2 IEEE papers (Wi-Fi 6E/7 Multi-AP & Multi-Link). MATLAB/Simulink modelling and PHY-MAC demonstrators.
DOI : 10.1109/INDIN45523.2021.9557495
DOI : 10.1109/ETFA52439.2022.9921700
M.Sc. in Telecommunications Engineering, University of Oviedo (2018–2020). Thesis: LTE-A/5G OFDMA receiver in MATLAB.
B.Sc. in Telecommunication Technologies and Services Engineering, University of Oviedo (2012–2018), Signal Theory & Systems track; undergraduate thesis on chipless RFID (Ka-band).
Erasmus at Linköping (VHDL audio equaliser; digital design projects).
