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· Page 3 / 17820Senior Design Verification Engineer Job Description: SV / UVM Test bench development and test cases coding. Code and Functional coverage analysis and closure. Work with team for verification closure. Experience with python or any other scripting language is a plus. Bus protocols AXI / APB / UART/ IJ
JD: Analog Circuit Design Engineer: 3+ years of experience in one of the following areas. Circuit design experience in analog/mixed signal CMOS circuits in High speed Memory interfaces (DDR3/4/5, LPDDR3/4x/5, GDDR5/6) or SerDes Interfaces (PCIe, MIPI, HDMI, USB, SATA etc ) or Design experience in hi
ADLINK TechnologyJob Summary: We are seeking a proactive Sales Engineer to support our business expansion in India. This role combines technical expertise with customer-facing sales activities, bridging the gap between the engineering and sales teams. The ideal candidate will have a solid technical background, stron
Experience: 6+ Yrs Skill: PCIe IP Verification We are looking for an experienced Design Verification Engineer with strong expertise in PCIe IP verification , SystemVerilog , and UVM . 🔹 Hands-on experience in PCIe protocol, VIP, coverage-driven verification & debugging 🔹 Strong skills in SV/UV
We are looking for contractors of around 6 to 8 years in “HW design” field with following requirements please send suitable profiles for screening. The ideal candidate will have a strong foundation in electronics and a proven track record in analyzing digital and power electronic circuits. A backgro
location:Plot No.1062-1063, GIDC-II, Sanand, Ahmedabad – 382170,Gujarat, India Job Responsibilities 1. Actively participate in various training programs organized by the company to enhance after-sales service capabilities and service quality. 2. Provide timely and effective after-sales service suppo
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Job Description We are looking for a smart engineer to join our Camera IoT SW team. You will be working on cutting-edge features to power the next generation of cameras in C
Position: AM/DM - Electrical Required Qualification & Certification: Degree – B.E./ B. Tech/ M. Tech in Electrical Engineering Experience: At least 5 years Location: Head Office, Noida Reporting To: Head of Department - Electrical Personal Qualifications: - Excellent Presentation & Communication ski
DFT Engineer (Staff/Sr. Staff) About the Role Responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug and diagnostics needs of the memories in design. Responsibilities - Work closely with the design, design-verification, and backend teams to ena
Job Title: Memory Layout Engineer Experience: 3+yrs Location: Bangalore Job Type: Full-time Industry: Semiconductors / VLSI / Memory Design Job Summary: We are looking for a Memory Layout Engineer with strong expertise in physical layout design of memory components such as SRAM, ROM, Register Files,
Sr. Emulation Engineer Job Description - 4-5 yrs of experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu) - Working knowledge of System Verilog & Verilog language semantics and compilation flows - Solid understanding on SOC architecture and AXI protocol
Experience: 4-5 Years Location: Bangalore/Hyderabad Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics Roles and Responsibilities Verilog, System verilog, UVM VHDL, UVVM Simulator exposure with VCS, Questa, Xcelium Proficient in simulation and HW languages Should be able to interpret
Job Description : - Continuous monitoring of system performance and identify potential issues before they impact users. - Experience working with Industry leading monitoring tools. - Respond to incidents related to monitoring systems, troubleshooting Level 1 issues and resolving issues promptly. - A
Job Description: - Develop and execute pre-silicon verification test plans for DFT features of the chip. Develop directed and random verification tests to validate the functionality. - Verify DFT design blocks and subsystems (such as MBIST, high speed IO PHY, fuse, clocks, reset) using complex SV or
Anchor Operating SystemAbout the job Anchor Operating Systems is seeking a QA Engineer for our Information Technology operation in Jaipur, Rajasthan. About The Opportunity As our QA Engineer, you will be a part of a team with a mission to build, innovate and maintain technology for distribution of the Anchor Operating Sys
DFT Engineer (Staff/Sr. Staff) About the Role Responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug and diagnostics needs of the memories in design. Responsibilities Work closely with the design, design-verification, and backend teams to enabl
Job Title: Production Engineer – Equipment Assembly (Radiology & Imaging Systems) Department: Production / Manufacturing – Radiology Division Location: Vapi, Gujarat Reports To: Production Supervisor / Production Manager – Radiology Systems Job Purpose: To perform and supervise cable connections, fi
Physical Design Engineer - Senior / Lead Job Description: Strong background in digital IC design , including floorplanning, placement, routing, clock tree synthesis, and optimization. Tools Expertise : Proficient in Innovus , ICC2 , and Fusion Compiler for place and route, timing closure, and physic
Job Title: H&E Image Analysis Scientist / Machine Learning Engineer- Spatial Omics (PhD) Experience: Freshers Location: Delhi Job Description: We are seeking a motivated PhD candidate interested in machine learning for histopathology image analysis. The candidate will contribute to developing and op
Job Title: H&E Image Analysis Scientist / Machine Learning Engineer- Spatial Omics (PhD) Experience: Freshers Location: Delhi Job Description: We are seeking a motivated PhD candidate interested in machine learning for histopathology image analysis. The candidate will contribute to developing and op
