Gate Level Simulation - 9+ job offers

Analog Devices

₹15,00,000 - ₹20,00,000 /year

Job Description Define and implement comprehensive verification strategies for complex ASIC designs. Develop robust unit and SoC level test benches using UVM , ensuring thorough design validation. Apply expertise in various aspects of digital verification, including constrained random verification,

Job Description Hands-On UVM at user level, pseudo and constrained random techniques, assertion-based verification techniques with System Verilog. Verification of analog interface is a value add along with ARM based subsystem, core sight, security subsystem verification exposure. 3rd party, industry

Analog Devices

₹12,00,000 - ₹16,00,000 /year

Job Description Own and deliver on design verification of complex Intellectual Property (IP) or Subsystem or complete full chip (SoC) level features and mixed signal subsystems. Collaborate with design, applications, product and test engineering teams to ensure the implementation meets both architec

Job Description We are seeking a results-oriented Senior Digital Verification engineer to join our team focusing on development of the next generation of ADI s Gigabit Multimedia Serial Link products delivering best-in-class solutions for in-car infotainment and advanced driver-assistance systems (A

Job Description Are you a highly skilled Formal Verification Engineer looking to make a significant impact across the entire product lifecycle Join Analog Devices in a senior role where you'll drive the formal verification of complex digital designs, from concept through to release. You'll collabora

Job Description Verification of complex ASIC chips and sub-systems using leading edge verification methodologies. Create verification plans for blocks and full chip by developing a thorough understanding of the design under test. Employ UVM/SystemVerilog based verification methodologies and use asse

Job Description Verification of complex ASIC chips and sub-systems using leading edge verification methodologies Define test plans, tests and verification methodology for block and chip level verification. Employ UVM/SystemVerilog based verification methodologies and use scoreboard, assertions, func

JD: Exp: 8+ Years Location: Bangalore “What you will do We are looking for someone to strengthen the ASIC Top level team with respect to GLS. We are currently developing two main dies to be instantiated in various configurations in different ASICs. One die consists of a huge number of DSPs and even

Object Technology Solutions

₹1,33,333 - ₹1,66,667 /year

*Role & responsibilities** Skill sets, experience, and qualifications needed for the role, such as **gate-level simulation**, verification, timing closures, and familiarity with Cadence tools. **Primary and Secondary Skills**: Clarification on the essential skills (e.g., GDS experience, timing c