657 job opportunities for timing analysis in India updated today
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· Page 1 / 33Role: STA Engineer Job Description Key Responsibilities: Develop, review, and maintain robust SDC constraints (clocks, I/O, generated clocks, timing exceptions). Perform block‑level and full‑chip STA using PrimeTime/Tempus and ensure timing closure across all MMMC scenarios. Own RTL synthesis (Desig
1.;;;; STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. 2.;;;; Timing analysis, validation and debug across multiple PVT conditions using Tempus. 3.;;;; Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. 4.;;;; Hands-on experi
ScaleFluxStatic Timing Analysis (STA) Lead Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology nodes. As a STA lead you will be working on PrimeTime based flow devel
Static Timing Analysis (STA) Engineer Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner
Position Overview We are seeking an experienced STA Lead with strong expertise in Static Timing Analysis for complex ASIC/SoC designs. The ideal candidate will be responsible for driving timing closure activities across block and full-chip level designs while collaborating closely with RTL, Physical
We are seeking an experienced STA Lead with strong expertise in ASIC timing analysis and timing closure across block and/or full‑chip designs. The role requires deep understanding of STA methodologies, constraints, ECO flows, and signoff checks , along with hands‑on experience using industry‑standar
ASIC Design and STA Engineer NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for hig
( www.enchargeai.com ) Staff Engineer, Static Timing Analysis (STA) Location: Greater Bengaluru Area (Hybrid-2 days office/3 days home) About Company: EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-m
Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad an
USTJob Title: STA Engineer (Static Timing Analysis) Experience Level: 5+ years Location: Pune, India Job Summary: We are looking for a skilled Static Timing Analysis (STA) Engineer to perform full‑chip and block‑level timing analysis for advanced SoC designs. The candidate will work closely with Design
MosChipJob Summary: We are seeking a Senior/Lead STA Engineer to ensure timing closure and sign-off for high-performance ASIC/SoC designs. The role requires deep expertise in timing analysis and optimization across multiple corners and modes. Key Responsibilities: Perform static timing analysis and timing
Project Role : Static Timing Analysis Engineer Project Role Description : Analyze and verify the timing of digital circuits to ensure they meet performance requirements under various operating conditions. Identify critical timing paths, perform timing optimizations, and resolve setup/hold violations
Design Engineer- PNR/STA Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Design Engineer: Place and R
Intel CorporationJob Details: Job Description: We are seeking an Entry Level Physical Design Engineer for a time bound assignment to support block level and chip level Physical Design execution on advanced technology nodes. The engineer will work as an individual contributor, under the guidance of senior Physical De
AMDTHE ROLE: As a member of the EPIC server soc team , you will help bring to life cutting-edge designs. As a member of the Physcial design/soc integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. T
QualcommGeneral Summary: As a global technology leader, Qualcomm is committed to pushing the boundaries of innovation. We are seeking a Senior Hardware Engineer specializing in Static Timing Analysis (STA) to join our world-class team. This role focuses on timing convergence for complex SoCs, IP blocks, and
Advanced Micro Devices (AMD)Setup ASIC QA flows for RTL design quality checks. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. Come up with clock constraints, false paths, multi-cy
Job Description Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance
QualcommJob Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a
Job Description Description We are seeking an experienced DFT Engineer to join our team in India. The ideal candidate will have a strong background in Design for Test methodologies and will be responsible for implementing DFT strategies for our integrated circuit designs. This role involves collabor
₹5,40,000 – ₹8,60,000per year
Estimation confidence: Low
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