3833 Vikram More
Electronics & Telecommunication Engineer
Talent
Pirangut, Pune, MaharashtraMember since July 17, 2026
Digital DesignVerilog HDLSystemVerilogUVM (Universal Verification Methodology)
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Digital DesignVerilog HDLSystemVerilogUVM (Universal Verification Methodology)
About
A highly organized and smart working individual, looking for a responsible position to gain practical experience in esteemed organization.
Education
BTech - Electronics & Telecommunication - Dbatu University Lonere (2022 - 2025)
Diploma - MSBTE (2020 - 2022)
12th - Maharashtra state board (2020 - 2020)
10th - Maharashtra state board (2018 - 2018)
Skills
Electronics & Telecommunication Engineer
