Aditya Kumar

Model microarchitecture and runtime performance in Python for a reconfigurable sparse CNN accelerator (PE Cluster Morphing Architecture) under a PhD mentor. Engineer a reconfigurable PE cluster hierarchy that switches between depthwise and pointwise modes at runtime for sparse compute scheduling. Quantify sparsity patterns, PE utilization, and latency bottlenecks across model configurations, feeding results directly into hardware architecture recommendations for the research team

Research Intern - IIT Roorkee

(2026-05)

• Model microarchitecture and runtime performance in Python for a reconfigurable sparse CNN accelerator (PE Cluster Morphing Architecture) under a PhD mentor.
• Engineer a reconfigurable PE cluster hierarchy that switches between depthwise and pointwise modes at runtime for sparse compute scheduling.
• Quantify sparsity patterns, PE utilization, and latency bottlenecks across model configurations, feeding results directly into hardware architecture recommendations for the research team

RADAR–Thermal Fusion ADAS - VLSID-2026 Design Contest

(2026-01 - 2026-01)

• Directed a 3-member team (Sillycon) through the VLSID-2026 ADAS track, defining the RADAR-thermal sensor fusion concept and dividing system design work across the team.
• Placed in the top 10 of teams in Round 1 of the Microchip innovation platform; built the FPGA-based system architecture and adapted a reference RTL accelerator for thermal pre-processing, integrated with a YOLOv5n model on the VectorBlox accelerator.

Bachelor of Technology - Electronics and Communication Engineering - Sardar Vallabhbhai National Institute of Technology, Surat (2024 - 2028)

Senior Secondary - RBSE - D.S Science Academy, Gangapur City (2024 - 2024)

Secondary - RBSE - D.S Science Academy, Gangapur City (2022 - 2022)