Adunuri Likitha

Striving for a position in a dynamic organization, leveraging my skills in Physical Design. Possess a comprehensive understanding of the physical design flow from RTL to GDS II, including (synthesis, partitioning, place and route, STA, signoff). Eager to contribute to the development of high quality and manufacturable integrated circuits within a team environment.

Advanced Physical Design Training at Maven Silicon Softech Pvt Ltd. (2024-08 – 2025-04)

Gained practical, project-based exposure to the entire ASIC flow, from RTL to GDSII, using Synopsys ICC2, Fusion Compiler, and PrimeTime.

• Hands-on experience in Floorplanning, Powerplanning, Placement, Clock Tree Synthesis (CTS), Routing, and timing analysis.
• Automated key processes with TCL and Python scripts, resolved timing closure challenges, addressed DRC/LVS issues, and optimised power and area.

DFT (Design for Testability) Training at Maven Silicon Softech Pvt Ltd. (2025-05 – 2025-07)

Completed post-physical-design training focused on industry DFT practices.

• Performed scan chain insertion, fault coverage analysis, boundary scan integration, and Embedded Deterministic Test (EDT) techniques using Tessent Shell.
• Enhanced testability of digital designs with hands-on tool flow for scan and test automation.

Bachelor of Technology in Electronics & Communication Engineering – Sri Chaitanya institute of technology & research (2021 – 2024)

Diploma in Electronics and Communication Engineering – Vaagdevi Polytechnic College (2018 – 2021)

Board of Secondary Education – New Raman High School (2017 – 2018)