Vijay Simha

Entry-level VLSI Physical Design Engineer with hands-on exposure to RTL-to-GDSII flow using Synopsys ICC2 with familiarity in ICC1 methodologies at 32nm technology. Understanding of floorplanning, placement, CTS, routing, congestion analysis, and basic static timing analysis (STA). Skilled in TCL scripting for basic automation. Seeking entry-level Physical Design roles.

VLSI Physical Design Engineer Trainee at Takshila Institute of VLSI Technologies (2025-05 – 2025-10)

• Followed complete RTL-to-GDSII physical design flow using Synopsys IC Compiler (ICC2) with hands-on exposure to ICC1 methodologies.
• Performed floorplanning, power planning, placement, clock tree synthesis (CTS), and routing; analyzed setup and hold timing violations during timing closure.
• Conducted congestion analysis, static timing analysis (STA), and DRC checks; applied TCL scripting for basic automation and debugging.

B.Tech in Electronics and Communication Engineering – Vardhaman College of Engineering (2021 – 2025)