Aman Rupain
M.Tech VLSI and Embedded Systems Student
Talent
Ghasiya Mahadev Srinagar Garhwal, UttarakhandMember since July 19, 2026
Bitcell DesignRTL to GDSDigital VLSI DesignSimulationLayout DesignVerilogSystemVerilogSpectreCadence VirtuosoIMCInnovusJasperGold
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Bitcell DesignRTL to GDSDigital VLSI DesignSimulationLayout Design
About
Guide: Dr. Anuj Grover
Experience
VLSI Design Intern - SCL (Semiconductor Laboratory) - Mohali, India
(2025-06 - 2026-07)
Guide: Dr. Anuj Grover
- SRAM Array & Bitcell Design: Engineered custom transistor-level SRAM macro cell arrays integrated with a replica column structure utilizing the SCL 180nm technology node; executed comprehensive bitcell static noise margin (SNM) stability analysis via butterfly curves.
- FOM Calculation & Sizing Optimization: Calculated and monitored critical Figures of Merit (FOMs) including power-delay product (PDP), read/write stability margins, and leakage parameters to drive optimal transistor sizing and balance Area-Power-Performance trade-offs.
- Multi-Corner PVT Troubleshooting: Identified and resolved complex circuit-level design challenges across multi-corner process variations, voltage fluctuations, and temperature ranges using simulation engines (Spectre) to confirm timing closure.
Education
M.Tech - VLSI and Embedded Systems - Indraprastha Institute of Information Technology (IIIT) Delhi (2024)
Bachelor of Technology - ECE - Hemvati Nandan Bahuguna Garhwal University (2019 - 2024)
High School - Shri Guru Ram Rai Public School (CBSE) (2016 - 2019)
Skills
M.Tech VLSI and Embedded Systems Student
