Ritvik Dwivedi

M.Tech VLSI student at IIIT Pune with academic exposure to Digital IC Design, ASIC Design Flow, Semiconductor Memory Design, RF IC Design, and IC Fabrication. Completed a hands-on RTL-to-GDSII workshop covering synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and timing analysis. Actively seeking professional internship opportunities in RTL Design, ASIC Design, and Physical Design.

MERN Stack Developer - Analyze Infotech

(2024-03 - 2025-04)

• Developed responsive, scalable web applications and engineered critical frontend components to improve runtime asset optimization.

Web Development & Data Science Intern - Birla Group & Code Clause

(2023 - 2023)

• Developed an interactive Sorting Algorithm Visualizer using HTML, CSS, and JS to demonstrate algorithm performance.
• Built a Face Recognition System using Python and OpenCV for real-time detection and identification.

M.Tech - VLSI - IIIT Pune (2025)

B.Tech - CSE - University of Lucknow (2020 - 2024)

Grade XII - CBSE - Kendriya Vidyalaya, Balrampur (2020 - 2020)