Ausaf Ahmad

Software Architect with 21+ years in EDA tools, Network-on-Chip (NoC) interconnect generation, high-level synthesis and compilers, with a hardware-software co-design focus. Led India R&D at Intel for configurable IP and NoC tools that generate RTL/netlist and IP-XACT collateral across multiple SoC programs. Earlier at Cadence, owned back-end RTL generation and FPGA flow for the CtoSilicon and Stratus HLS compilers.

Deep C++ and compiler-internals background (IR design, front-end/back-end, optimization), with working knowledge of AMBA CHI/ACE/AXI, IDI, SystemC/TLM2.0 and RTL. Independently designing hybrid AI plus deterministic architectures (LLM, GNN, RL) for EDA netlist generation and compilers.

Software Architect, India R&D Team Lead at Intel Corporation (2019-12 – 2026-05)

Configurable IP Tools and Network-on-Chip Interconnect IP | C++, TCL, RTL | Linux, Windows

• NoC Tool (team of 12): led India R&D for NoC RTL/netlist and collateral generation connecting multiple hosts (IPs, cores, memory) on SoC; designed internal data structures for net connectivity among module instances.
• IP Configuring Tool (team of 4): architected TCL/C++ tool for IP-to-IP and IP-to-SoC integration, replacing a 6+ month manual process and shortening time-to-market for multiple production SoCs.
• Designed a configurable Intermediate Representation (IR) at the interface-abstraction layer, separating interface-level connectivity from port-level wiring so one architecture supports multiple RTL/SystemVerilog generation strategies.
• Built a language-agnostic output layer (pretty-printer) on the IR to generate RTL, SystemVerilog and SystemC without per-language generation logic.
• Designed a hierarchical grouping abstraction: users define hierarchy with simple commands, and the tool unfolds it to full RTL hierarchy.
• Added an IR-level lint checker for connectivity errors before RTL generation, catching integration failures earlier.
• Reused the core IR for the NoC netlist project, cutting delivery time by about 40%; unified per-IP regression scripts into one shared flow.
• Hired and mentored junior engineers, owned task breakdown and reviews, and served as technical contact for internal customer teams.

Senior Principal Software Engineer at Cadence Design Systems (2010-12 – 2019-11)

Stratus HLS (team of 14, 2014–2019) and CtoSilicon (CtoS) HLS (team of 12, 2010–2014) | C++, SystemC | Linux

• Owned the back-end RTL/model generation module of CtoS: turned customer requirements into specs and designs, estimated effort, and resolved customer-filed issues (CCRs) within committed deadlines.
• Architected the FPGA synthesis flow supporting Xilinx Vivado and Intel/Altera (about 2 years); previously ASIC-only, opening a new market segment.
• Led the front-end migration from the EDG parser to LLVM/Clang across both HLS compilers, unifying divergent codebases.
• Built SystemC generation for CtoS, previously limited to behavioral RTL.
• Owned front-end language translation, elaboration and optimization modules; kept two back-end subsystems and the front end at zero critical field issues for 5 years through clean APIs and rigorous testing.

Lead Engineer at Samsung India Software Operations (2008-09 – 2010-11)

GLSL (OpenGL ES 2.0) shader compiler for GPUs | C++ | team of 4

• Built an optimizing GLSL compiler for vertex and fragment shaders: GLSL 1.0.16 parser, front-end and back-end optimizations, code generation, pattern matching and register scheduling.
• Chose a proprietary front end over LLVM to protect IP and meet delivery timelines; set up per-check-in regression testing; supported integration into the OpenGL ES library shipped on Samsung devices.

Project Lead at NECHCL System Technologies (2007-05 – 2008-09)

• Led C++ static analysis tool (Varvel): C Language Processor (CIL), C++-to-C lowering and a C/C++ file merger on the EDG front end; designed the IR bridge from the C++ front end to the legacy C back end. Teams of 2–5; handled client communication.

Engineer Level II at Covansys (PayPal) (2006 – 2007)

• Built Global Security Center redesign and Linked Restrictions features (C++/Java/XML/SQL).

Software Engineer at ACME Technologies (2004 – 2006)

• ANSI C cross-compiler for an 8-bit microcontroller (ccu8, OKI Electronics): register allocation, assembly generation, pointer handling, peephole and code-hoisting optimizations; moved the compiler from disk-based two-pass to in-memory single-pass; built compiler test automation.

M.Tech in AI/ML (Weekend Programme) – IIT Jodhpur (2026 – 2028)

M.Tech in Microelectronics (WILP) – BITS Pilani (2017 – 2019)

M.C.A. – Hamdard University, Delhi (2001 – 2004)

B.Sc. – University of Lucknow (1996 – 1999)