ASIC Physical Design Engineer
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Results-driven Physical Design Engineer with a strong foundation in ASIC design, place and route, and timing analysis. Proficient in industry standard EDA tools like Innovus and Tempus , with hands-on experience in f loorplanning, CTS, and STA. Skilled in scripting (TCL) for design automation and optimization. Dedicated to delivering high- performance, power-efficient chip designs while ensuring DRC compliance.
EDA Tools: Cadence Innovus Implementation System ,Tempus Timing Signoff Solution
Languages: TCL , Python , Verilog
Concepts: Physical Design Flow, Floorplanning, Placement, Routing, Clock Tree Synthesis, Static Timing Analysis (STA), Power Analysis , DRC , ECO optimization
Operating Systems: Linux, Windows
Certification ASIC Physical Design ∥ IcLabs IN, Bangalore Education ( August, 2024– Present ).
B.Tech Electronics and Communication Engineering (CGPA:8.26) APJ Abdul Kalam Technological University.
