ASIC Physical design engineer
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From a curious ECE student fascinated by microchips to an ASIC Physical Design enthusiast with real-world project experience—I’ve been on a deep and rewarding journey through the world of VLSI.
I specialize in Physical Design, Verification, and Static Timing Analysis with hands-on exposure to advanced nodes like 7nm and 45nm. I've completed end-to-end implementations of industry-grade designs including a Leon Processor, DTMF decoder, and MSP430 microcontroller. My toolkit includes Cadence tools—Genus, Conformal, Innovus, Tempus, and Voltus—and a strong grasp of RTL to GDSII, Floorplanning, Placement, CTS, Routing, and Signoff processes.
What sets me apart is not just my technical ability, but my commitment to optimizing every step of the flow—whether it's minimizing congestion, balancing clock skew, or tightening timing slack in high-performance blocks. I back this with a solid foundation in Verilog HDL, TCL scripting, CMOS fundamentals, and digital electronics.
I recently completed an advanced certification from Entuple Technologies and earned several Cadence digital badges. My goal is to join a forward-thinking semiconductor company where I can grow into a Physical Design Engineer contributing to high-speed, low-power SoC designs.
If you're looking for a passionate and detail-driven VLSI engineer who's eager to learn, collaborate, and solve real-world design challenges—I’d love to connect. Let's build silicon that powers the future!
Results-driven ASIC Physical Design Engineer with expertise in RTL to GDSII flow, advanced nodes (7 nm–90 nm), and tools like Cadence Innovus,Innovus , Genus,Voltus,s, Voltus , Conformal. Skilled in floor planning, STA, CTS, routing, ECOs, and PPA optimization, with proven success intiming closure and IR-drop mitigation. Currently pursuing M.Tech in VLSI and Embedded Design, aiming to apply technical skills and innovationto deliver high-performance ssolutions.tor solutions
