Chandan M
Research Intern
Talent
BengaluruMember since August 24, 2026
VerilogSystemVerilogTCL scriptingGenusStatic Timing Analysis
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VerilogSystemVerilogTCL scriptingGenusStatic Timing Analysis
About
Designed a CMOS delay-locked loop-based clock multiplier for stable clock generation, focusing on jitter reduction. Analyzed delay-line behavior across PVT corners and optimized control loop stability, area and power consumption.
Experience
Research Intern at Indian Institute of Science (2026-01 – Present)
- Designed a CMOS delay-locked loop-based clock multiplier for stable clock generation, focusing on jitter reduction.
- Analyzed delay-line behavior across PVT corners and optimized control loop stability, area and power consumption.
ASIC Design Intern (Chip Tape-Out) at Centre for Hardware Acceleration and Chip Security (2025-06 – 2025-08)
- Implemented lightweight block cipher, SIMON, using SCL 180nm PDK. This included constrained synthesis, TCL scripting, I/O planning, STA, and physical design with clean DRC/LVS for MPW-IV shuttle (C2S0116).
- Achieved 100 MHz operating frequency, 10 mW power consumption, and 0.608 mm² area under design constraints.
Education
Bachelor of Technology in Electronics & Communication – PES University (2022 – 2026)
Skills
Research Intern
