Gayathri N R

M.Tech VLSI Design engineer with hands-on UVM testbench architecture, SVA assertions, APB/AXI protocol verification, and DFT scan insertion. Physically validated RISC-V SoC on Altera Cyclone IV FPGA achieving 250× latency speedup. Designed 71 nW Delta-Sigma ADC in 45nm CMOS using Cadence Virtuoso. Published author — NCACCS'26 journal + IEEE 2024 conference.

VLSI Design Intern - Apex I Sys - Coimbatore

(2025-06 - 2025-07)

• Designed UVM-style testbenches for combinational and sequential digital circuits; authored SVA assertions using interfaces and OOP constructs, improving assertion coverage.
• Completed end-to-end RTL design and verification of 4-bit ALU and Traffic Light Controller using industry-standard EDA tools.

M.Tech - VLSI Design - Government College of Technology, Coimbatore (2024-07 - 2026-05)

B.E. - Electronics and Communication - Rajalakshmi Institute of Technology, Chennai (2020 - 2024)