J Ruthra Moorthy
Research Intern – VLSI Hardware Security
Talent
ChennaiMember since September 23, 2026
Verilog HDLPythonUARTSPIVivadoMATLABCommunication
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Verilog HDLPythonUARTSPIVivado
About
Designed a Secure ALU in Verilog HDL using XOR Logic Locking and FSM-based Key Locking. Developed RTL modules and verified them through simulation, synthesis, and functional testing in Xilinx Vivado.
Experience
Research Intern – VLSI Hardware Security - SRM University AP
- Designed a Secure ALU in Verilog HDL using XOR Logic Locking and FSM-based Key Locking.
- Developed RTL modules and verified them through simulation, synthesis, and functional testing in Xilinx Vivado.
VLSI Security and AI Intern - SECENAI Semiconductors and Test Solutions Pvt. Ltd.
- Researched hardware security architectures including Physical Unclonable Functions (PUF).
- Built a Python-based adversarial attack framework to evaluate AI-driven vehicle detection systems and contributed to secure drone research.
Education
Bachelor of Technology (B.Tech) - Electronics and Communication Engineering - SRM University AP (2023-01 - 2027-12)
Tamil Nadu Higher Secondary Examination (2022-01 - 2022-12)
Tamil Nadu Secondary Examination (2021-01 - 2021-12)
Skills
Research InternVLSI Hardware Security
