Lead Engineer - Silicon validation Engineer at HCLTech (2021-12 – Present)
- Experienced in pre-silicon and post-silicon validation, driver development, and bare-metal programming.
- Validated IP functionality based on feature specifications to ensure design accuracy and performance.
- Performed pre-silicon validation using FPGA platforms to identify and reduce defects prior to post-silicon testing.
- Strong ability to analyze and interpret technical specification documents for effective validation planning.
- Hands-on experience in developing test scripts, writing driver code, and performing debugging to ensure system reliability.
Firmware Validation Engineer at Falcon Mesa - Intel/Altera (2022-04 – 2025-10)
- Performed regression and stress testing in Altera Falcon Mesa Agilex7 FPGA devices across multiple firmware releases and manual debugging.
- Generated SOF (SRAM Object Files) for configuration testing.
- Used configuration interfaces like JTAG, AVST, and AS modes to program FPGA devices and validated its functionality based on the firmware released. Published validation reports to client stakeholders.
- Used PythonSV 2.0 based regtest framework to execute regression, stress validation, Analyzed logs, debugged failures, and ensured issue resolution.
- Familiar with ION session manager, RealVNC Viewer, Perforce, System console, sof generation using Quartus tool and virtual understanding of FPGA board setup and experience in debugging the board issues.
- Collaborated with firmware and hardware teams for issue resolution.
