Pandurang Kulkarni

Result-driven Post-Silicon Validation & Firmware Validation Engineer with 2.8+ years comprehensive experience specializing in Intel client/server platforms. Proven track record in execution of end-to-end platform board bring-up, BIOS/UEFI configuration, CPU validation, and power/performance optimization. Expert in verifying high-speed interfaces (PCIe, USB, Thunderbolt) and discrete external Graphics (dGFX).

Advanced technical capabilities in provisioning secure remote infrastructure utilizing Intel EMA and MeshCommander. hardware-level debugging, and systemic trace analysis, targeting zero-defect transitions from silicon to production.

Associate I – Semiconductor Product Validation Engineer - UST (Client: Intel Corp) - Bengaluru, India

(2023-11 - 2026-08)

• Platform Board Bring-up & Validation: Owned and successfully executed phase-0/1 hardware board bring-up for nextgeneration Intel client and server platform reference designs, ensuring board stability, power-on sequences, and bootstrapping configurations.
• BIOS/UEFI & CPU Validation: Formulated test cases and validated BIOS/UEFI firmware code stacks. Verified critical CPU sub-systems including power management states (C-states, P-states), thermal throttling, and x86 register configurations against architectural specifications.
• Power & Performance (PnP): Analysed and optimized platform power distribution and performance vectors under variable synthetic workloads, benchmarking throughput efficiencies across distinct silicon stepping's.
• High-Speed Subsystem Validation: Directed comprehensive subsystem compliance and validation matrix for External Graphics (dGFX), Thunderbolt (TBT), and Type-C USB interfaces; checked Link Training, lane degradation, hot-plug capabilities, and error recovery injection.
• Storage Interface Verification: Validation lead for high-speed storage ecosystems, conducting signal integrity and protocol correctness validation across NVMe, SATA SSD, legacy HDD, and embedded UFS storage mediums.
• Remote Infrastructure Setup: Engineered, deployed, and managed custom on-premise centralized servers configured with Intel EMA (Endpoint Management Assistant) and MeshCommander, enabling secure, out-of-band remote bare-metal provisioning and debug operations across engineering labs.
• Hardware Debugging & Telemetry: Utilized Intel ITP for active low-level hardware state probes, register dumps, and execution halts. Capturing and triaging platform panic logs and serial console traces utilizing PuTTY and Tera Term to isolate root causes between silicon, firmware, and hardware layouts.
• Firmware Security & Compliance: Executed CHIPSEC validation suites to identify platform firmware vulnerabilities, secure boot misconfigurations, and flash write-protections. Designed custom test content utilizing hardware-passthrough Virtual Machine (VM) environments to safely isolate platform firmware vulnerabilities, secure boot misconfigurations, and flash write-protections Utilized FWTS (Firmware Test Suite) to eliminate ACPI and kernel boot space mismatches.

Bachelor of Engineering (B.E) - Electrical and Electronics Engineering - Shetty Institute of Technology (2023)