Loga Priya
Senior Verification Engineer
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About
4+ Years of Experience in Frontend Design Verification. Proficient in developing and debugging UVM components from scratch, enabling reusable verification environments. Experienced in creating detailed test plans and test cases for IP and SOC-based verification.
Hands-on expertise in creating and managing constraint-random testbenches to ensure comprehensive coverage and thorough validation. Strong working knowledge of assertion-based verification for design behavior monitoring and validation. Experienced in functional, code, and assertion coverage analysis to achieve verification closure.
Experience
Senior Verification Engineer - SocBridge semiconductors - Bangalore, India
(2021-07)
Education
Bachelor's - Electronics and Communication Engineering - KSR Institute for Engineering and Technology (2015-06 - 2019-04)
