Mekala Anjikumar

FPGA Design and Verification Engineer with 2+ years of hands-on experience in RTL design and validation using Xilinx 7-Series and UltraScale+ platforms. Proficient in Verilog, SystemVerilog, and Xilinx Vivado, with strong expertise in implementing and validating high-speed protocols like I2C, UART_16550, MIPI I3C, and eSPI. Skilled in MicroBlaze soft-core integration, block-level design, and board-level debugging on platforms such as Genesys2 and Nexys-A7.

Adept at collaborating with clients, mentoring junior engineers, and delivering reliable and optimized digital systems.