S. Hari
VLSI Design Verification Engineer
Talent
Hyderabad, TelanganaMember since August 18, 2026
VerilogSystem VerilogRTL DesignAXIAPBDDR4Questa SimUVMMATLABSVIDSMBUSRAL model
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VerilogSystem VerilogRTL DesignAXIAPB
About
Motivated and detail-oriented VLSI engineer with training in Verilog and System Verilog. Proficient in Verilog, System Verilog, UVM, and industry-standard tools like Questa Sim. Seeking an entry-level opportunity in VLSI Design Verification to apply digital design, RTL, and verification skills in semiconductor projects.
Strong
Knowledge of AMBA protocols (APB4, AXI4, CHI), LPDDR4 and SVID.
Education
B-Tech in ECE – PVKK Institute of Technology (2018-01 – 2022-01)
Intermediate – Narayana junior College (2016-01 – 2018-01)
School – M.J.P.A.P.B.C.W.R School (2016-01)
Training in RTL Design & Verification – VLSI First
Skills
VLSI Design Verification Engineer
