Nitish Singh

Worked on RTL design and development of I3C Protocol IP for high-speed serial communication interfaces.

Performed Clock Domain

Crossing (CDC) analysis to identify and mitigate metastability and synchronization issues.

Conducted

Lint checks and participated in RTL sign-off activities to ensure code quality and design rule compliance.

RTL Design Intern - STMicroelectronics

(2025-07 - 2026-06)

• Worked on RTL design and development of I3C Protocol IP for high-speed serial communication interfaces.
• Performed Clock Domain Crossing (CDC) analysis to identify and mitigate metastability and synchronization issues.
• Conducted Lint checks and participated in RTL sign-off activities to ensure code quality and design rule compliance.
• Analyzed, reported, and debugged RTL errors and flag violations during verification and sign-off stages.
• Collaborated with design and verification teams to improve IP reliability and maintain design documentation.

M.Tech - EVLSI - Netaji Subhas University of Technology (2024 - 2026)

B.Tech - ECE - Chhatrapati Sahu Ji Maharaj University (2023)

Board - Class XII - St. Joseph International School (2019)

Board - Class X - Urmil Unique Central Academy (2016)