Pranali Sarate

Detail-oriented VLSI Engineer with hands-on experience in RTL Design, Digital Design, and pre-silicon Design Verification (DV) using Verilog and SystemVerilog. Proficient in architecting robust UVM testbenches, implementing constrained-random verification, and writing SystemVerilog Assertions (SVA) to ensure maximum functional coverage.

Advanced Design Verification and RTL Trainee at VLSI for All Pvt. Ltd (2025-04 – Present)

• Enhanced simulation accuracy by 20% through the implementation of advanced verification techniques.
• Supported design and testing of digital circuits, resulting in a 15% increase in created efficiency
• Implemented a System Verilog verification environment using UVM, accelerating the identification of 15 critical bugs in the design.
• Applied constrained-random methodologies to uncover edge-case hardware defects, increasing overall verification efficiency and design reliability.

Design Verification Intern at Capgemini Engineering (2022-07 – 2023-09)

• Established verification environment utilizing System Verilog to enhance testing efficiency
• Upgraded existing test bench environments, leading to a 25% reduction in verification time.
• Planned and applied constrained-random system Verilog test benches using UVM.

Test Engineer at Dhoot Transmission Private Ltd (2021-02 – 2022-01)

• Enhanced laser printing operations for power transmission components, achieving a 7% reduction in material waste through optimized parameter settings and improved material handling procedures within the first three months.
• Boosted knowledge of laser printing techniques for industrial applications.

BTech in E&TC – Dr. Babasaheb Ambedkar Technological University (2021)

Class XII – Rastramata Indira Gandhi College (2017)

Class X – S.B High School (2015)