Raj Raj

Physical Design Graduate Intern at Intel Corporation, worked on advanced-node technologies including N3(3nm), 7nm, and Intel 18A, with hands-on experience in Physical Design Verification, Layout Verification, and debugging complex layout issues.

Physical Design Engineering Graduate Intern (AI SoC) at Intel Corporation (2025-07 – Present)

• Performed block-level physical verification including DRC, LVS, ERC, and Antenna checks using Mentor Calibre, Synopsys Fusion Compiler, IC Validator, ensuring layout correctness prior to tape-out.
• Debugged complex layout violations - metal shorts, opens, spacing, density, base layer, and antenna violations - in high-congestion regions of 18A AI SoC blocks, reducing re-spin risk.
• Checked design collaterals and ran APR flow checks; identified root causes when run flows failed and performed re-sign to resolve blocking issues.
• Developed TCL-based automation for batch DRC/LVS job submission, log file parsing, and error report generation, improving verification efficiency.
• Collaborated with senior engineers to debug placement, routing, and DRC issues on N3 AI SoC blocks, improving block quality and reducing dependency on late-stage ECOs.

Engineering Intern at Power Grid Corporation of India Ltd. (2022 – 2022)

• Performed testing and maintenance of 400/220 kV transformers and substation protection systems.
• Analysed SCADA operations and electrical fault reports to improve system reliability.

Teaching Assistant at National Institute of Technology Goa (2024 – 2025)

M.Tech in VLSI Design – National Institute of Technology Goa (2024 – 2026)

B.Tech in Electrical Engineering – University Institute of Technology, University of Burdwan (2019 – 2023)