Sr. Verification Engineer | CPU DV | RISC-V (IMFDC) | LSU | CPU µArch, Caches, Coherency
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With 4 years of experience as an ASIC Verification Engineer, I specialize in developing verification environments from scratch. I possess strong expertise in protocols such as CHI and APB, and am proficient in writing test cases, debugging, and problem-solving. My skill set includes comprehensive knowledge of Digital Circuits, Verilog, System Verilog (SV), UVM, Computer Architecture, and RISC-V.
Additionally, I have understanding of Functional Coverage and hands-on experience with standard simulation tools.
Senior Engineer (Level 1) at Einfochips (An Arrow Company) (2026-07 – Present)
Verification Engineer at Scaledge Technology (2022-09 – 2026-06)
Verification Trainee at Scaledge Technology (2022-03 – 2022-09)
Electrical Project Engineer at Anand Enterprises (2018-05 – 2019-10)
Electrical Engineer at CPL Electric (2016-07 – 2017-09)
M.Tech in Power System – NIT Patna (2022)
B.Tech in Electrical and Electronics Engineering – Kurukshetra University (2015)
Intermediate – Loyola High School (2010)
SSC – Loyola High School (2008)
