Ranjith S

• layouts Design from Leaf cell to global routing with design constraints consideration. 
• All Memory Validation Checks (like DRC, LVS, DFM, CDTOOL, ERC  etc.) & Extraction.
• Handling the multiple design in parallel.
• Having knowhow of track-based layout. 
• Having experience to work in 28nm, 32nm, 45nm, 65nm, 90nm Technology.

Total Year of Experience: ~ 4 Years (Custom Layout Design)

• Mask Design Engineer with Western Digital since MAR 2018 to FEB 2022.
• Trainee with RV VLSI since Jan 2017 to Jan 2018 : Worked mostly on SRAM 

Bachelor of engineering

Bachelor of Engineering (EEE)

PG diploma : Layout design in SRAM 28nm