Karthik Pindi

I am a passionate Electronics and Communication Engineer with a strong foundation in VLSI.

Having graduated from Amrita Vishwa Vidyapeetham, Coimbatore 2024 Batch with an 8.4 CGPA.

I have gained valuable hands-on experience in Analog Layout Design through my 6-month internship at Texas Instruments.

My expertise lies in designing layouts for circuits such as LDOs, Comparators, PassFETs, and Standard Cells like NAND, NOR, and D Flip-Flops for 65nm and 130nm technologies.

I have a keen interest in VLSI, layout optimization techniques, and troubleshooting DRC and LVS related issues.

Currently exploring opportunities in the Analog Layout Domain, I am focused on enhancing my skills in advanced and lower node technologies like FinFETs.

I have a 6-month internship experience at Texas Instruments, I worked on layouts for circuits such as LDOs, Comparators, PassFETs, and logic gates (NAND, NOR, D Flip-Flop, Inverter) in 65nm and 130nm technologies, gaining in-depth knowledge of layout optimization, matching techniques, and addressing challenges like antenna effects and latch-up.

I am proficient in critical signal routing, ensuring CMRR, minimizing clock skew, and optimizing propagation delay in layout designs. With a strong focus on power management ICs and next-gen technologies like FinFETs, I am actively preparing for opportunities with leading organizations

I graduated in 2024 with a Bachelor’s degree in Electronics and Communication Engineering from Amrita Vishwa Vidyapeetham, Coimbatore with a CGPA of 8.43.