Shreya Raj

Aspiring VLSI Engineer with a strong foundation in digital electronics, Verilog HDL, and VLSI design concepts. Hands-on experience in RTL design, combinational and sequential circuit modelling, simulation, and verification using Verilog. Familiar with ASIC design flow, FPGA-based implementation, and semiconductor fabrication fundamentals. Eager to apply practical knowledge and creativity to real-world problems.

Green Synthesis of Nanoparticles

• Conducted research on eco-friendly synthesis of nanoparticles using jackfruit peel.
• Performed comparative analysis, simulations, and graphical interpretation.
• Gained exposure to nanotechnology concepts relevant to semiconductor materials.

B.E. in E.C.E – St. Joseph's College of Engineering