Swaathi Ravichandran

Designed a 5-stage Verilog pipeline for FPGA quadrature encoder decoding on a Zynq-7000 SoC Built a 32-bit position engine with sub-pulse interpolation, boosting resolution nearly 150,000x Wrote a full simulation suite in Icarus Verilog, covering 8 regression tests and 800 data points

Research Intern at National Institute of Technology, Tiruchirappalli (2026-05 – 2026-07)

• Designed a 5-stage Verilog pipeline for FPGA quadrature encoder decoding on a Zynq-7000 SoC
• Built a 32-bit position engine with sub-pulse interpolation, boosting resolution nearly 150,000x
• Wrote a full simulation suite in Icarus Verilog, covering 8 regression tests and 800 data points
• Synthesized and deployed the design on real Zynq-7000 hardware with zero timing violations
• Built an on-chip signal emulator and ARM firmware to test the pipeline without physical sensors
• Matched hardware output to theoretical predictions down to the clock cycle, using a custom LED debug method

Summer Intern at Defence Research and Development Organisation (DRDO) (2025-05 – 2025-07)

Interned at CVRDE-DRDO on the Arjun MBT gun control system.

• Proposed a PMSM-based drive to replace hydraulics, cutting current draw from 300A to 70A
• Analysed 3 analog circuits and digitised them via Tustin's bilinear transform at 1 kHz
• Implemented discrete filters in C on a TMS320F28377S DSP (200 MHz)
• Modelled a PMSM in dq-frame using Clarke-Park transforms; tuned cascaded PI controllers via pole-zero cancellation in MATLAB/Simulink
• Designed 2 friction-compensation methods, reducing stick-slip tracking delay by 80%

B.Tech in Instrumentation and Control Engineering – National Institute of Technology, Tiruchirappalli (2023-08 – 2027-05)