VLSI Design Intern | RTL Design, ASIC Design & Digital Architecture
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I am a Electronics and Communication Engineering student with hands-on experience in RTL design, digital architecture, and ASIC/FPGA synthesis flows. Designed and implemented multi-module digital systems — including an AI accelerator SoC and GPU-style compute architecture — in Verilog and System Verilog. Experienced with Vivado for FPGA-targeted synthesis, Yosys for gate-level analysis, and Verilator for functional verification.
Consistently focused on building well-structured, verified hardware from HDL down to the gate level.
B. Tech - Electronics and Communication Engineering - Institute of Engineering and Management, Kolkata (Newtown Campus) (2024-01 - 2028-01)
