Suma Sri Pothala

Physical Design Engineer (Fresher) with a B.Tech in ECE (CGPA: 8.21) and specialized backend VLSI physical design training at Sumedha Institute. Demonstrates hands-on expertise across the complete RTL-to-GDSII ASIC flow—including macro-aware floorplanning, multi-layer power network synthesis (PG mesh), placement optimization, Clock Tree Synthesis (CTS), global/detail routing, and timing signoff closure on TSMC 28nm using Synopsys IC Compiler II (ICC2) and Design Compiler (DC). Proficient in managing Multi-Corner Multi-Mode (MCMM) setup/hold timing slack closure (useful skew, ECO buffering), IR drop analysis, basic Tcl scripting for flow automation, and achieving zero-overflow DRC/LVS clean signoff on macro-intensive blocks up to 345K+ cells.

VLSI Physical Design (CVA6 Processor Project) at Sumedha Institute of VLSI (2026-03 – 2026-05)

Block-Level Physical Design on ~300K Cells, 24 Hard Macros, Clock: 1.5 ns (667 MHz), Node: TSMC 28nm, Tool: Synopsys ICC2

• Implemented a 9-layer PG grid (M1 std cell rails, M4/M5 mesh, M6/M7 stripes, M8/M9 top grid) with custom VIA12–VIA56 rules, meeting target IR drop limits across PVT corners.
• Executed fly-line-guided macro placement for 24 hard macros with placement halos and routing channels to eliminate pin-access and routing congestion.
• Synthesized multi-clock domain CTS with NDRs and clock shielding, balancing sink latencies across 24 macro boundaries.
• Closed setup and hold timing across MCMM corners using useful skew, region placement, and targeted ECO buffer insertion at 1.5 ns.
• Resolved routing congestion hotspots using cell density tuning and detour strategies, achieving signoff with zero DRC/LVS errors.

VLSI Physical Design (TILE Project) at Sumedha Institute of VLSI (2026-06 – 2026-08)

SRAM-Intensive Block Physical Design on ~345K Cells, 18 SRAM Macros, Clock: 1.7 ns, Node: TSMC 28nm, Tools: Synopsys DC, ICC2

• Defined SDC constraints covering multicycle paths, path grouping (r2r/i2o/r2m/m2r), clock uncertainty, and fanout/transition limits.
• Executed macro-aware floorplanning with keepout regions, pin guides, and concurrent clock-data (CCD) optimization during physical synthesis.
• Performed SI-aware routing, redundant via insertion, filler cell insertion, and metal density fill to comply with foundry density rules.
• Achieved signoff timing closure (WNS: +0.02 ns, TNS: 0) with clean DRC/LVS physical verification.

VLSI Design Intern at Technotran Company (2024-06 – 2024-08)

• Completed training on CMOS fundamentals, digital logic concepts, and RTL-to-GDSII design flow.

Bachelor of Technology in Electronics & Communication Engineering – Raghu Institute of Technology (2021 – 2025)