Sumbul Fatima
VLSI undergraduate skilled in RTL to Bitstream SoC design, ASIC Design Flow implementation
Talent
Greater NoidaMember since June 1, 2026
Verilog HDLDesignFSM DesignPYNQ-Z2Synopsys DC shellPrimeTimeRTL Simulation
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Verilog HDLDesignFSM DesignPYNQ-Z2Synopsys DC shell
About
VLSI undergraduate skilled in RTL to Bitstream SoC design, ASIC Design Flow implementation seeking a RTL design intern role to contibute to RTL development, high performance processor work
Experience
Volunteer, Tech-ECE Domain at IEEE Student Branch, JIIT (2024-01 – Present)
- Assisted in organizing technical workshops, mentoring 50+ first-years students on verilog and digital logic, facilitating hands-on learning like Arithmetic Logical Unit.
- Orchestrated logistics 5+ campus events, increasing student participation by 20 percent
Education
Bachelor of Technology in EE(VLSI) – Jaypee Institute of Information Technology (2027-12)
Skills
ASIC Design Flow implementation
