Yash Dubey
Internship in VLSI Design flow (RTL to GDS-II)
Talent
VaranasiMember since June 4, 2026
ASICFPGAOverview of VLSI Design FlowStatic Timing AnalysisBasic Concepts for Physical Design
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ASICFPGAOverview of VLSI Design FlowStatic Timing AnalysisBasic Concepts for Physical Design
About
Hardware Modeling Using Verilog RTL Synthesis & Verification Floor planning, clock tree synthesis, routing
Experience
Internship in VLSI Design flow (RTL to GDS-II) - NIELIT, Centre of Excellence (CoE) in Chip Design - Noida
(2025-06)
- Hardware Modeling Using Verilog
- RTL Synthesis & Verification
- Floor planning, clock tree synthesis, routing
Education
Bachelor of Technology - ECE with Major Specialization in VLSI Design - Shri Mata Vaishno Devi University (SMVDU) (2024 - 2028)
Skills
Internship in VLSI Design flow (RTL to GDS-II)
