Internship in VLSI Design flow (RTL to GDS-II)
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Hardware Modeling Using Verilog RTL Synthesis & Verification Floor planning, clock tree synthesis, routing
Internship in VLSI Design flow (RTL to GDS-II) - NIELIT, Centre of Excellence (CoE) in Chip Design - Noida
(2025-06)
Bachelor of Technology - ECE with Major Specialization in VLSI Design - Shri Mata Vaishno Devi University (SMVDU) (2024 - 2028)
