H M Pedersen

Strong technical expertise in lead, architecture, design and verification tasks of ASIC and FPGA design products in multicultural teams and international companies. I have in-depth knowledge of GSM/3G/LTE/5G and Ultra Wide Band standards and implementation as well as Ultrasonic/Radar designs. Outstanding skills in problem analysis and capability development.

Well-versed in supervising cross-functional teams and completing first-time-right ASIC tape-outs. Extensive experience in SoC and VLSI design and IP block implementation including high level synthesis. Instrumental in managing ASIC and verification requirements resulting in high-quality verification closure with vManager or VC Execution Manager in a UVM framework.

Excellent skills in establishing regression testing flows and verification plan development. Verification experience with SystemVerilog / UVM workflow / formal verification / UPF power aware verification / gate level simulation / Certitude Functional Qualification System. Verification methods applied for advanced mixed signal SoC projects.

Design and verification process control, method development, verification visibility and development of project KPIs. I am proactive, I have attention to detail and timely execution. I am looking forward to working with technology driven companies.

ASIC Consultant - IMEC

(2024-07)

• Setup vManager flow within IMEC with Jenkins Plugin
• vPlan, constraint-random verification, coverage, CRF regressions for IMEC Gen4 UWB modem
• Setup Stratus High level synthesis flow within IMEC
• Setup Github CI/CL flow for UWB
• IEEE 802.15.4a HRP UWB modem improvements: re-architecture and completely rewritten in SystemC, end to end; implemented with high level synthesis. Quantization and resource-sharing refactor delivering ¼ of the Gen4 size (area) while improving PER.
• Soft-decision Viterbi (6-bit) with traceback depth 12; survivor memory and fixed-point widths tuned for robustness and latency using Matlab to Stratus flow.
• symbol timing and acquisition refined with Kalman filter and demodulator re-architecture.
• Verification lead of the Seneca project in the last 2 months before tape-out.

LEAD ENGINEER — ASIC Consulting - TII

(2022-07 - 2024-07)

• Design and verification/validation of true random number generator using a generalised ring oscillator and a Linear Hybrid Cellular Automata.
• HLS design and verification of AES accelerator.
• AES-GCM design and verification with minimalistic area and masked leakage; lab validation of side-channel leakage (ChipWhisperer).
• Xilinx SoC implementation with MicroBlaze platform and secure IP peripherals.
• Constraint-random verification and SoC design of GF 22 nm ASIC for side-channel analysis.
• Created Cadence Genus synthesis and Conformal flow; UPF 2.1 power-aware RTL simulations and GLS.
• Principal reviewer of RTL and UVM verification framework of cryptographic hardware library.

SENIOR PRINCIPAL ASIC SPECIALIST CONSULTANT — ASIC Consulting - imec – Holst Centre - remote

(2020-11 - 2022-07)

• UWB ASIC: Design and verification of sample-rate converters, de-spreaders, and Viterbi decoders; top-level verification and schedule adherence.
• DARE6 radiation IP: clock-tree re-architecture; internal SRAM timing engines; reliability/performance analysis on imec IC-link DARE65 nm platform.

ASIC VERIFICATION CONSULTANT — ASIC Consulting - Xilinx - remote

(2020-05 - 2020-11)

• 5G NR PRACH UVM verification: test plan, sequences, constraint-random verification, coverage, CRF regressions.
• Prepared written summaries of simulations, coverage analysis; achieved 100% functional and assertion coverage.

VERIFICATION LEAD CONSULTANT — ASIC Consulting - Ericsson - Stockholm/remote

(2018-03 - 2020-03)

• Shark/Radon/Krypton 5G control subsystems: introduced CRV techniques; significant improvements in functional/code coverage.
• Maintained functional coverage groups and UVM scoreboards; streamlined vManager vPlan regressions (Hansoft Scrum).

EXPERT ASIC CONSULTANT - Huawei Technologies - Leuven, BE

(2017-03 - 2018-03)

• Top-level verification of 5G Direct Mode TX; UVM register-layer testbench (cycle & bit-accurate versus C++ reference); Jenkins CI.
• Re-architected digital up-sampling chain and clock-tree → ~50% power reduction; HLS synthesis of DPD; formal verification of IP blocks.

SENIOR PRINCIPAL ASIC SPECIALIST CONSULTANT - Frontier & EnSilica - Oxford, UK

(2015-09 - 2017-03)

• ARM Cortex-M3 mixed-signal SoC (battery charger): target IC spec, architecture design spec, IP selection; area/power tracking; DFT strategy.
• NFC-powered smart card SoC (Cadence BBE16EP DSP): requirements, memory optimization, clock-gating/DVFS options; Jenkins CI; FPGA prototyping.
• Sensium Healthcare WBAN 802.15.6 SoC: RTL for PMU, clock, AES-CCM, security engine, low-power heart-rate accelerator; SRAM arbitration; APB/ADC/RF interfaces.

PRINCIPAL ENGINEER - Micron Technology - Manchester, UK

(2013-12 - 2015-09)

• PCIe-connected AHCI/NVMe SSD virtualization; NVMe error management and high-availability architecture.
• Verification of AHCI virtualization layers on FPGA; advanced NVMe SSD controller design.

SENIOR ASIC SPECIALIST - Nokia → Renesas - Copenhagen, DK

(2007-11 - 2013-12)

• Wireless Modem SoC front-end tech lead (GSM/LTE/3G, DigRF). Viterbi decoders (enhanced SISO and list); low-power optimizations.
• Power estimation/reduction (PowerTheater, PowerArtist); UPF power-aware sims (VCS); Jenkins test automation; Certitude TB/suite qualification.
• Synopsys flow (DC/PrimeTime/PX) and Magma (Conformal/Blast); clock-tree optimization and power-gating; multi-site coordination.

M.Sc. - Synthetic Aperture Radiometer - DTU

Research Assistant - Fast signal processing on FPGAs for Medical 3D Ultrasound - DTU