Devika Ajith

Familiar with AMBA Bus,SPI,Video protocols etc.Experienced FPGA design engineer with 2 years of experience

Experienced in RTL Integration, Synthesis, FPGA Implementation across Xilinx platforms using Vivado, Digital Logic Design, Industry standard protocols,Functional simulations, Hardware .Testing , Design Debugging and Basics of Static Timing Analysis on FPGA .

MTech in VLSI and Embedded systems from Kerala Technological University with a GPA of 8.4.