16 verification opportunities in Paya Lebar updated today
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AmbitionRole Overview This role leads and drives a high-performing design verification team responsible for delivering robust, zero-defect SoC and ASIC solutions. The position focuses on advancing verification methodologies across increasing design complexity while ensuring high-quality, on-time execution t
OMNIVISIONDescription As a design verification engineer, you will be part of a passionate verification team that is constantly pushing the limits – developing and deploying state‑of‑the‑art verification methodologies in ever‑increasing design complexities, from UVM, C/C++ co‑simulation, system emulation to mi
Uni ConnectA leading technology firm in Singapore is looking for a design verification engineer. In this role, you will join a dedicated team to develop advanced verification methodologies, aiming for zero defects across complex designs. Applicants should ideally have experience in UVM verification and a relev
Advanced Micro DevicesA technology company is seeking an experienced Verification Engineer in Singapore to lead verification efforts for cutting-edge server memory products. The ideal candidate will have extensive knowledge of DDR interfaces and memory protocols, such as DDR5 and LPDDR5, and skills in SystemVerilog and U
BYTEDANCE PTE. LTD.About Us Founded in 2012, ByteDance's mission is to inspire creativity and enrich life. With a suite of more than a dozen products, including TikTok, Lemon8, CapCut and Pico as well as platforms specific to the China market, including Toutiao, Douyin, and Xigua, ByteDance has made it easier and more
BYTEDANCE PTE. LTD.A major tech company in Singapore is looking for a Video Codec Design Engineer to join their fast-growing team. The role involves designing hardware accelerators for video encoding and processing, requiring strong expertise in SystemVerilog and UVM methodology. Candidates should have over three year
AmbitionRole Overview This role leads and drives a high-performing design verification team responsible for delivering robust, zero-defect SoC and ASIC solutions. The position focuses on advancing verification methodologies across increasing design complexity while ensuring high-quality, on-time execution t
BITMAINJob Responsibilities: 1. Responsible for module verification and system verification of SOC digital circuits; 2. Write verification specifications, test plans, and test cases according to the design specifications; 3. Set up the verification platform and environment; debug problems encountered in si
Espressif SystemsWe are looking for a Senior Design Verification Engineer to work on Espressif's next-generation wireless and AI-capable SoCs. You will work closely with RTL designers and chip architects, and provide technical leadership within a small verification sub-team. Job Responsibilities Define verification
Barrington JamesPrincipal FPGA Verification Engineer Role Overview The Principal FPGA Verification Engineer is responsible for leading the development and implementation of comprehensive verification and validation strategies for FPGA-based systems. This role focuses on ensuring the functionality, performance, inte
Keysight TechnologiesAbout the Job: We are seeking a passionate and innovative student who would like to join our dynamic Quantum R&D team in CSG Enterprise and Sv. You will be working closely with the SRE team on creating a Test Report Generation Framework. The work involves building, testing and deploying the framewor
IntelliProJob Title: ASIC/SoC Design Verification Engineer Position Type: Full-Time, Fully Onsite Location: Singapore OR San Jose, CA USA Salary Range / Rate: Base S$100,000-S$180,000(Singapore) Base $150,000-$220,000(US) Visa Sponsorship: Open to Singapore EP Sponsorship and US work visa sponsorship based on
Summary: We are seeking a skilled Chip Physical Verification CAD Engineer to join a team focused on enabling physical verification sign-off flows and solutions for advanced SoC (System-on-Chip) designs. This role involves working on cutting-edge technology nodes and ensuring design accuracy and comp
OMNIVISIONAs a Design Verification Manager, you are expected to carry out the following responsibilities. Be in-charge of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM
OMNIVISIONCommitment Period: Jan 2026 onwards (Full-time Internship, min. 6 months) Job Description As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasi
OMNIVISIONDescription: As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mi
As a Design Verification Manager, you are expected to carry out the following responsibilities. Be in-charge of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM
MaxLinear Inc.Responsibilities MaxLinear is seeking a SOC Verification Engineer to join our VLSI group. You will be responsible for pre-silicon RTL verification of block, subsystem and top level SOC. With deep understanding of design architecture and meticulous attention to details, you will develop reusable test
· Analyze complex verification and digital design problem. · Develop testbenches, · Drive/develop ASIC verification flows andscripts. · Create Verification architecture. · Work with the RTL Design team to ensurefunctional correctness and coverage. · Support silicon bring-up and diagnostics. · Suppor
As a Design Verification Manager, you are expected to carry out the following responsibilities. Be in-charge of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM
MaxLinearResponsibilities MaxLinear is seeking a SOC Verification Engineer to join our VLSI group. You will be responsible for pre-silicon RTL verification of block, subsystem and top level SOC. With deep understanding of design architecture and meticulous attention to details, you will develop reusable test
*Role Description** A Data Verification Assistant ensures the accuracy, completeness, and integrity of organizational data by reviewing and validating information across systems and processes. Responsibilities include: Reviewing and verifying data entries for accuracy, consistency, and compliance wi
THE ROLE: We are looking for an adaptive, self-motivative Design Verification (DV) engineer to join our growing PLL team. As a key contributor, you will be part of a leading team that drives and improves AMD's ability to deliver the highest quality, industry-leading technologies to the market. The D
In this role you will be part of a world-class IC design team responsible for the development and deployment of software solutions for a revolutionary computing system, which will reduce the energy consumption of AI processing by two orders of magnitude over conventional digital solutions. This will
BITMAINJob Responsibilities Responsible for module verification and system verification of SOC digital circuits; Write verification specifications, test plans, and test cases according to the design specifications; Set up the verification platform and environment; debug problems encountered in simulation t
$43,000 – $68,000/year
Estimation confidence: Low
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