Digital Technology Integration jobs in Hsinchu

Company Qualcomm Semiconductor Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Product and Test Development Engineering (PDTE) is looking for Digital Test Engineers who will create test solutions in support of New Product Introduction (Silicon Validati

Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help creat

Qualcomm

Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a

Job Description 5G modem architecture and digital circuit design Whole chip clock, test, and reset plan. Low power digital design SoC chip integration from RTL to gate level including timing closure and testability Requirement Better to have chip integration experience (5+ years) Familiar with front

Best NanoTech

*Foundry Engineering – Process Integration / Yield / Technology (Multiple Levels)** *Location:** Hsinchu / Tainan / Taiwan *Experience:** 7–20+ years *Function:** Semiconductor Manufacturing / Foundry Interface Role Overview Opportunities are available for engineers with experience in *semiconductor

*Job Description** Chip/SoC integration Package/Floorplan integration *Requirement** Familiar with digital IC design Familiar with IC design flow Familiar with PERL or Pynthon Familiar with frontend EDA tools (DCG/LEC/TV/CCD/PrimeTime) Experience with Package/Floorplan integration

*Job Description** SoC chip integration from RTL to gate level including timing closure and testability Whole chip DFT structure planning and design Whole chip timing review and closure sign-off Design methodology and integration flow improvement Chip TOP IO and floorplan planning and TOP glue circu

*Job Description** Own the top-level integration of internal and third-party IPs into SOC or FPGA platform. Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan. Work closely with architect to define specification, suppor

*Job Description** High Speed digital design implementation Integration from RTL to gate level, including flow QC, timing closure and issue analysis & solving Signoff on design with mixed-signal interface Design methodology and integration flow improvement *Requirement** Familiar with front-end

工作說明 1.規劃訓練活動及維護訓練發展紀錄維護、相關報表產出 2.依產業人才發展或組織人力需求，進行課程設計與規劃、並驗證學習成果與辦理成效 3.執行公司內各部門訓練需求調查，並制定年度訓練計劃及預算 4.負責編撰合適的訓練教材，並依據實際需求評估與外部專業機構合作或自行規劃訓練課程 5.實施員工的訓練計劃(管理/專業/通識類)，並進行相對應的訓練成效評估，以確保達成訓練成效 6.建立員工訓練歷程檔案，作為組織內人才調度的參考依據 7.規劃各組織階層的訓練藍圖，並執行管理技能培訓，以確保人才晉升管理職位能順利勝任 8.依據員工發展需求，制定員工職業生涯發展方案並實施，建立人才儲備 9.規劃及

MediaTek

*Job Description** Own the top-level integration of internal and third-party IPs into SOC or FPGA platform. Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan. Work closely with architect to define specification, suppor