Hsinchu今日更新的7個ic verification職缺機會
個職缺
Job Description The candidate will conduct functional verification of the RF transceiver circuit design at various stages—from individual circuit blocks to the complete system operation—using behavioral models during the design process. Requirement Qualifications The ideal candidate should possess a
Job Description The candidate will conduct functional verification of the RF transceiver circuit design at various stages—from individual circuit blocks to the complete system operation—using behavioral models during the design process. Requirement Qualifications The ideal candidate should possess a
Job Description The candidate will conduct functional verification of the RF transceiver circuit design at various stages—from individual circuit blocks to the complete system operation—using behavioral models during the design process. Requirement Qualifications The ideal candidate should possess a
*Job Description** (請留意：為加快面試安排時間，僅限定投遞5個職缺)我們在找這樣的你：對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣；勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。 *Requirement** (投遞履歷請附上大學/研究所成績單) 歡迎具備以下經驗及專長的你：修習過影像相關課程與數位IC相關課程，如：訊號處理、數位影像處理、視訊壓縮、數位IC設計、數位IC設計實驗、計算機組織、計算機結構；Verilog
ASPEED Technology**Job Description:*** Develop and execute *verification plans** for SoC/ASIC/IP designs, including defining strategy, writing test plans, and architecting scalable verification environments. Build and enhance *UVM-based verification environments** , ensuring reusability and maintainability of driver
*Job Description** Co-work with algorithm, digital/analog design, firmware, AI tool teams. 0+ ~ 10+ Years Experience in: Agentic AI Workflow/Tool Evaluation/Deployment Data Center & High-Speed SerDes Design Verification Plan & Project Execution Automotive Design Verification Plan & Proje
*Job Description** (請留意：為加快面試安排時間，2026校招僅限定投遞5個職缺)我們在找這樣的你： 資工/資管/電子/電機/電信/通訊/電控相關研究所背景，對行動通訊、無線及寛頻連結、家庭娛樂晶片解決方案有濃厚興趣的2026年應屆畢業生。 勇於表達意見，以團隊成功為目標，面對困難不輕易放棄，總是在想更好的做法，擁有創新及不斷學習的精神。 聯發科技邀請您，與全球最頂尖的菁英一同合作，彼此激盪最新的創意與解法，共同挑戰每一個不可能。 *Requirement** 修習過影像相關課程與數位IC相關課程，如：訊號處理、數位影像處理、視訊壓縮、數位IC設計、數位IC設計實驗、計算機組
*Job Description** Work with design teams to do performance sign off in pre-silicon stage ESL platform and simulation/emulation technology development. Model development (includes behavior modeling/ cycle approximate modeling) *Requirement** Familiar with Verilog/SystemVerilog/C++/Perl/Python Famili
*Job Description** RTL design Digital IC design Digital multimedia system design SOC Integration Bus architecture design *Requirement** Familiar with digital IC design Experienced in SOC architecture or FPGA verification Experienced in video/image processing is a plus Experienced in bus architecture
*Job Description** (Internal transfer preferred, offers a platform for growth, optimizing cross-product workflow) Personality: leadership, proactive, lead the team or task force to complete tough missions Scope: Digital SOC design/integration, includes Package, Floorplan, IOMUX, Test-mode design Clo
*Job Description** Chip/SoC integration Package/Floorplan integration *Requirement** Familiar with digital IC design Familiar with IC design flow Familiar with PERL or Pynthon Familiar with frontend EDA tools (DCG/LEC/TV/CCD/PrimeTime) Experience with Package/Floorplan integration
*Job Description** Architecture design and digital circuit design. RTL implementation and verification. SoC chip integration from RTL to gate level including timing closure and testability Design methodology and integration flow improvement *Requirement** Familiar with digital IC design and FPGA emu
工作說明 Driver程式與Firmware程式開發 FPGA與IC驗證 自動化驗證流程開發 協助FAE釐清並解決客戶問題 安全演算法開發與驗證 教育程度 大學 碩士 擅長工具 熟悉C語言與Firmware程式開發 具備RTOS概念 熟悉FPGA與IC驗證流程 熟悉I2C、SPI等......protocol 熟悉LA、示波器等......操作 管理責任 否 工作經驗 1-3 年 3-5 年
工作說明 1. Driver程式與Firmware程式開發2. FPGA與IC驗證3. 自動化驗證流程開發4. 協助FAE釐清並解決客戶問題5. 安全演算法開發與驗證教育程度 大學碩士擅長工具 1. 熟悉C語言與Firmware程式開發2. 具備RTOS概念3. 熟悉FPGA與IC驗證流程4. 熟悉I2C、SPI等......protocol5. 熟悉LA、示波器等......操作管理責任 否工作經驗 1-3 年3-5 年
Novatek Microelectronics Corp.We are seeking a Design Verification Engineer experienced in building UVM-based verification environments and verification models. The candidate will define verification plans, implement UVM testbenches and VIPs, collect function and code coverage, analyze uncovered points, and drive closure to ensu
Iron MountainAt Iron Mountain we know that work, when done well, makes a positive impact for our customers, our employees, and our planet. That’s why we need smart, committed people to join us. Whether you’re looking to start your career or make a change, talk to us and see how you can elevate the power of your
Iron MountainAt Iron Mountain we know that work, when done well, makes a positive impact for our customers, our employees, and our planet. That’s why we need smart, committed people to join us. Whether you’re looking to start your career or make a change, talk to us and see how you can elevate the power of your
$480,000 – $765,000/año
估算信賴度：Low
Estimate based on market data for Hsinchu. Actual salaries may vary depending on experience, company, and area.
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