Asic jobs in Irvine

Job Description: ASIC Verification Engineer High Speed Interconnect Product (HSIP) Group The Opportunity Broadcom is the global leader in semiconductor solutions, and our High Speed Interconnect Product (HSIP) team is at the heart of the AI and data center revolution. We design the industry’s lowest

Sarum LLC

$8,667 - $10,400 /year

Job Overview We are seeking a dynamic and detail-oriented ASIC CAD/EDA Flow/Methodology Developer to join our innovative team. This role offers an exciting opportunity to shape the design and verification workflows for advanced integrated circuits, ensuring seamless collaboration across design, veri

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual

Broadcom

You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: Architecting block and full-chip verification environments using HVLs (UVM) and constrained ran

Marvell Technology

Your Team, Your Impact As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOC) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the

Marvell Technology

Your Team, Your Impact As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOC) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the

CyberCoders

$16,667 - $25,000 /year

*Job Title:** Sr. ASIC/SoC Architect *Job Location:** San Jose, CA or Irvine, CA *Compensation:** $240K - $300K base Depending on experience plus stock options! *Requirements:** Microarchitecture, Processor Architecture, Memory, Cache Subsystems, NoC, Interconnects *Position Overview** We are seekin

Broadcom

$9,000 - $14,400 /year

*Please Note:** *1. If you are a first time user, please create your candidate login account before you apply for a job.** *2. If you already have a Candidate Account, please Sign-In before you apply.** ## **Job Description:** We are looking for an ASIC Implementation Engineer with demonstrated expe

*Job Title:** Senior ASIC/SoC Physical Design Engineer *Job Location:** San Jose, CA or Irvine, CA *Compensation:** $150K - $250K base DOE plus equity *Requirements:** ASIC/SoC Physical Design, RTL-to-GDSII, Place and Route (P&R), Static Timing Analysis (STA), Synopsys, FinFET, Power Analysis *P

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. *PRINCIPAL ASIC DES

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. *PRINCIPAL ASIC DES

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. *SR. ASIC DESIGN VE

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. *SR. ASIC DESIGN VE

Chelsea Search Group

Senior/Staff ASIC Design Engineer Key Responsibilities Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis Optimize designs for performance, power, and area (PPA) requirements Per

Sigmaways Inc

We are seeking a Senior SoC/ASIC Physical Design Engineer to drive physical design activities to successful closure by collaborating closely with RTL and cross-functional engineering teams. In this role, you will develop, refine, and implement cutting-edge flows and methodologies that optimize perfo

*Company Description** At WD, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible. At our core, WD is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve bee

Chelsea Search Group

Senior or Staff ASIC Design Engineer Key Responsibilities: • Design and implement digital circuits using HDL (Verilog/ System Verilog) • Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis • Optimize designs for performance, power, and area (PPA) requir